Non-volatile memory (NVM) or non-volatile storage, is generally a semiconductor storage device that is able to retain the stored information even after the removal of a power source. Most types of magnetic computer storage devices (e.g. hard disks, floppy disks, and magnetic tape), optical discs, and early computer storage methods such as paper tape and punch cards, maintains its memory even after power is lost. However, semiconductor non-volatile memory typically comprises EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable and Programmable Read Only Memory) and flash memory. NVM is typically used for the task of secondary storage, or long-term persistent storage.
Electrically addressed systems include, but are not limited to, EPROM, EEPROM, and flash memory. Although different types of electrically addressed systems have different structures, the general method of writing data and deleting data is similar. The structures include arrays of individual memory cells that are able to be programmed to hold a logic level 1 or 0. These individual memory cells are able to be floating gate transistors or SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) transistors, such as in the case of EEPROMs, or NOR and NAND logic gates, such as in the case of FLASH memory.
FIG. 1A shows a SONOS memory device 50. The device 50 is a modified transistor, having a gate 55, drain 56 and source 57 that are generally etched from a metal deposited on a substrate 59 to form a memory transistor. In SONOS memory devices, data, in the form of charge, is stored and is retained when the power is removed. The SONOS memory device has a polysilicon control gate 52 and a nitride layer 51 that functions as a charge storage element. The nitride layer 51 is electrically isolated by surrounding oxide including an oxide layer 53 and a gate oxide layer 60. The control gate 52 is the external control terminal of the memory transistor 50.
In the case of a n-type SONOS MOSFET, when in operation, with no charge on the nitride layer 51, the device 50 acts normally, and a voltage applied to the control gate 52 causes current to flow as in a standard MOSFET. When the nitride layer 51 is charged, the charge shifts the MOSFET threshold voltage so that, with the same control gate voltage, current does not flow. In the case of a p-type SONOS MOSFET, when in operation, with no charge on the nitride layer 51, the device 50 has no current flow when a voltage is applied to the control gate 52 as in a standard p-MOSFET. When the nitride layer 51 is charged, the charge shifts the MOSFET threshold voltage to positive so that, with the same control gate voltage, current starts to flow. Charging the nitride layer 51 is generally accomplished by grounding the source terminal, biasing the drain terminal, and placing sufficient voltage on the control gate 52 such that charge tunnels through the oxide 60 to the nitride layer 51. This is typically called channel-hot-electron (CHE) programming. Alternatively, SONOS devices can also be programmed with a sufficient gate-to-substrate voltage. This mechanism is known as “Fowler-Nordheim” (FN) Tunneling. A reverse gate-to-substrate voltage clears the charge from the nitride layer 51 by causing the charge to dissipate into the substrate 59. In the case of n-type SONOS, charges in the nitride layer 51 can also be cleared by a negatively biased control gate 52 and a positively biased source/drain. This mechanism is known as “Hot Hole Band-to-Band Tunneling”.
In terms of CHE programming, charging the nitride layer 51 and thereby storing data in the memory device 50 is able to be achieved by a process known as hot carrier injection. The memory cell 50 is programmed by charging the nitride layer 51 via the injection of hot-electrons from the pinch-off region of the drain 56. The hot-electrons get their energy from the voltage applied to the drain 56 and the source 57 of the memory cell 50. They are accelerated by a lateral electric field along the channel into even higher fields surrounding the drain depletion region. Once these electrons gain sufficient energy they surmount the energy barrier between the silicon substrate and the silicon dielectric layer or gate oxide and are trapped in the nitride layer 51. With a positive voltage applied to the drain 56 and a positive voltage applied to the gate 55, electrons are pulled toward the nitride layer 51 and then trapped in the nitride of an n-channel memory cell.
FIG. 1B shows a floating gate memory device 150. The device 150 is a modified transistor, having a gate 155, drain 156 and source 157 that are generally etched from a metal deposited on a substrate 159 to form a memory transistor. In floating gate memory devices, data, in the form of charge, is stored and is retained when the power is removed. The floating gate memory device comprises a polysilicon first gate 151 that is known as a “floating gate” because it is buried within a gate oxide 160 and a dielectric 153 beneath a polysilicon control gate 152. In some devices, this dialectric 153 is known as the inter-polysilicon dialectric (IPD). The IPD 153 isolates the floating gate 151 and is able to be oxide or oxide-nitride-oxide (ONO). The control gate 152, which is the second gate, is the external control terminal of the memory transistor 150.
In operation, with no charge on the floating gate 151, the device 150 acts normally, and a voltage applied to the control gate 152 causes current to flow as in a standard MOSFET. When the floating gate 151 is charged, the charge shifts the MOSFET threshold voltage so that, with the same control gate voltage, current does not flow. Charging the floating gate 151 is similarly accomplished as charging the nitride layer 51 in the SONOS memory device of FIG. 1A, for example using FN Tunneling or hot carrier injection.
As the person of ordinary skill having the benefit of this disclosure will recognize, both FN Tunneling and hot carrier injection are functions of energy fields formed by voltages applied to any of the gate or drain of a memory transistor. As a result, variation in the process to form these devices, thereby causing variation in the size of the gate, drain, or width of the control gate, nitride layer, floating gate, oxide layers or dielectric, or any like component in a similar memory device, will cause thresholds required to trap electrons in the SONOS device or the floating gate device to change. In application, these thresholds are parameters in end products that must conform to pre-determined requirements, since an end user will place a device having many millions of memory transistors or other cells into some terminal interface which will either write data, erase data, or read data by applying signals of pre-determined magnitudes. Should a device have different thresholds, the applied signals will not trigger a write, read, or erase function, and as a result a device having non-conforming thresholds is discarded as a manufacturing failure.
FIG. 1C shows common thresholds for writing to and erasing from electrically addressed NVM. A program (PGM) margin level 100 is the level at which a signal must be presented to an individual memory cell or unit in order for that unit to hold a binary or logic “1” or “high.” The signal is able to be presented in the form of cell current or applied voltage Vg, also known as threshold voltage. An erase (ERS) margin level 110 is the level at which a signal must be presented to an individual memory cell or unit in order for that unit to hold a binary or logic “0” or “low.” In general, devices are tested in a process known as wafer sort. Individual die, each having a large number of individual memory cells thereupon, are tested whole as a plurality of probes contact the I/O of each individual die to ascertain whether the individual memory cells have PGM and ERS levels that conform to predetermined requirements. A typical test result 101 determines whether an actual level 101A of a signal which satisfies a PGM operation was sufficient to complete a PGM step into an individual memory cell. The PGM level 101A is above the PGM margin level 100 and therefore the PGM test during wafer sort would be a pass. Also, an actual ERS level 101B is below the ERS margin level 110. As a result, the die exhibiting these characteristics is generally a “pass” or conforming unit. However, as is well known, silicon wafers can suffer process variations. The extremes of these variations are known as process corners. The variation is caused for example, by variations in deposition depth, metal layer thickness, or any host of reasons during the wafer fabrication process. A process corner causing a fast PGM and slow ERS 102 has a PGM level 102A that passes, but a ERS level 102B that fails. However, the difference between the ERS level 102A and the PGM level 102B is the same as the difference between the PGM level 101A and the ERS level 101B. A process corner causing a fast ERS and slow PGM 103 has a passing ERS level 103B but a failing PGM level 103A. Again, there is a healthy window between the ERS level 103B and the PGM level 103A, which is the same as the difference between the PGM level 101A and the ERS level 101B. Because of the wide window between ERS and PGM program levels, the device can be viable for use. However, due to the rigid PGM margin level 100 and ERS margin level 110, the devices fail and the wafer suffers lower overall yield. The PGM level 100 and ERS margin level 110 are generally set by a universal “trimming” step wherein the levels 100 and 110 are programmed as fixed values into a lot of wafers. What is needed is a method and system for dynamic trimming so that individual die can have varying margin levels, thereby better coping with process variations and tolerances to processes having wide variations from the onset, allowing for the use of cheaper, more widely varying processes while still leading to increased product yield.